The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2014
Filed:
Dec. 15, 2010
Yuji Ando, Tokyo, JP;
Takashi Inoue, Tokyo, JP;
Kazuki Ota, Tokyo, JP;
Yasuhiro Okamoto, Tokyo, JP;
Tatsuo Nakayama, Tokyo, JP;
Kazuomi Endo, Tokyo, JP;
Yuji Ando, Tokyo, JP;
Takashi Inoue, Tokyo, JP;
Kazuki Ota, Tokyo, JP;
Yasuhiro Okamoto, Tokyo, JP;
Tatsuo Nakayama, Tokyo, JP;
Kazuomi Endo, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer, a channel layer, a barrier layer, and a spacer layeris formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer, the channel layerhaving a compressive strain, and the barrier layerhaving a tensile strain, and the spacer layerhaving a compressive strain are laminated on a substratein this order. The gate insulating filmis arranged on the spacer layer. The gate electrodeis arranged on the gate insulating film. The source electrodeand the drain electrodeare electrically connected to the channel layerdirectly or via another component.