The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2014

Filed:

Mar. 22, 2012
Applicants:

Noriaki Mukai, Toride, JP;

Masaru Mitsumoto, Ryugasaki, JP;

Makoto Homma, Katori, JP;

Inventors:

Noriaki Mukai, Toride, JP;

Masaru Mitsumoto, Ryugasaki, JP;

Makoto Homma, Katori, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/44 (2006.01); H05K 3/34 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H05K 3/30 (2006.01);
U.S. Cl.
CPC ...
H05K 3/3436 (2013.01); H01L 21/563 (2013.01); H01L 24/75 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 23/564 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/75272 (2013.01); H01L 2224/75281 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/8388 (2013.01); H01L 2224/83951 (2013.01); H01L 2224/9211 (2013.01); H01L 2924/01082 (2013.01); H05K 3/303 (2013.01); H05K 2201/0129 (2013.01); H05K 2201/10674 (2013.01); H05K 2201/10977 (2013.01); H05K 2203/167 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/014 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/83191 (2013.01); H01L 2224/73104 (2013.01);
Abstract

Solder bumps are formed on a plurality of electrode parts of a printed substrate and a semiconductor chip is loaded on the printed substrate via the plurality of solder bumps. In this case, a thermoplastic film is prepared as an underfill that covers a surface of the printed substrate on which the solder bumps are formed. In the film, parts corresponding to the solder bumps are removed and a peripheral edge of a part on which the semiconductor chip will be loaded has a protruded form. After the printed substrate has been covered with the film, the film is bonded onto the board and the semiconductor chip is loaded on the printed substrate and carried into a reflow furnace. In the reflow furnace, heat and pressure are applied to fuse the solder bumps.


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