The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 23, 2014
Filed:
Mar. 27, 2012
William F. Clark, Jr., Essex Junction, VT (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Terence B. Hook, Jericho, VT (US);
Junjun LI, Williston, VT (US);
Theodorus E. Standaert, Clifton Park, NY (US);
Thomas A. Wallner, Pleasant Valley, NY (US);
William F. Clark, Jr., Essex Junction, VT (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Terence B. Hook, Jericho, VT (US);
Junjun Li, Williston, VT (US);
Theodorus E. Standaert, Clifton Park, NY (US);
Thomas A. Wallner, Pleasant Valley, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.