The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2014

Filed:

Sep. 26, 2012
Applicant:

Mentor Graphics Corporation, Wilsonville, OR (US);

Inventors:

Rami Fathy Salem, Windsor, CA;

Haitham Mohamed Eissa, Cairo, EG;

Ahmed Arafa, Milpitas, CA (US);

Sherif Hany Mousa, Cairo, EG;

Abdelrahman ElMously, Wilsonville, OR (US);

Walid Farouk Mohamed, Cairo, EG;

Mohamed Amin Dessouky, Cairo, EG;

Assignee:

Mentor Graphics Corporation, Wilsonville, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 17/5063 (2013.01);
Abstract

Aspects of the invention relate to techniques for detecting and correcting electrical hotspots in a layout design for a circuit design comprising an analog circuit. Layout parameters for device instances associated with electrical constraints are first extracted. Based on the extracted layout parameters, electrical parameter variations for the device instances may be computed to identify one or more electrical hotspots in the layout design. A sensitivity analysis of the one or more electrical hotspots is performed to generate repair hints. Based on the repair hints, the layout design is adjusted.


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