The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2014
Filed:
Apr. 16, 2014
Wei-sheng Lei, San Jose, CA (US);
James S. Papanu, San Rafael, CA (US);
Aparna Iyer, Sunnyvale, CA (US);
Brad Eaton, Menlo Park, CA (US);
Ajay Kumar, Cupertino, CA (US);
Wei-Sheng Lei, San Jose, CA (US);
James S. Papanu, San Rafael, CA (US);
Aparna Iyer, Sunnyvale, CA (US);
Brad Eaton, Menlo Park, CA (US);
Ajay Kumar, Cupertino, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
Approaches for hybrid laser scribe and plasma etch dicing process for a wafer having backside solder bumps are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof and corresponding arrays of metal bumps on a backside thereof involves applying a dicing tape to the backside of the semiconductor wafer, the dicing tape covering the arrays of metal bumps. The method also involves, subsequently, forming a mask on the front side of the semiconductor wafer, the mask covering the integrated circuits. The method also involves forming scribe lines on the front side of the semiconductor wafer with a laser scribing process, the scribe lines formed in the mask and between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, the mask protecting the integrated circuits during the plasma etching.