The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2014

Filed:

Feb. 09, 2010
Applicants:

Huang-yu Chen, Zhudong Township, TW;

Yuan-te Hou, Hsin-Chu, TW;

Fung Song Lee, Banciao, TW;

Wen-ju Yang, Hsin-Chu, TW;

Gwan Sin Chang, Hsin-Chu, TW;

Yi-kan Cheng, Taipei, TW;

Li-chun Tien, Tainan, TW;

Lee-chung LU, Taipei, TW;

Inventors:

Huang-Yu Chen, Zhudong Township, TW;

Yuan-Te Hou, Hsin-Chu, TW;

Fung Song Lee, Banciao, TW;

Wen-Ju Yang, Hsin-Chu, TW;

Gwan Sin Chang, Hsin-Chu, TW;

Yi-Kan Cheng, Taipei, TW;

Li-Chun Tien, Tainan, TW;

Lee-Chung Lu, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 27/02 (2006.01); H01L 23/528 (2006.01); H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 2924/0002 (2013.01); H01L 23/5286 (2013.01); H01L 27/11807 (2013.01);
Abstract

A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.


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