The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2014

Filed:

Sep. 04, 2012
Applicants:

Vladimir Mikhalev, Boise, ID (US);

Jim Fulford, Meridian, ID (US);

Yongjun Jeff HU, Boise, ID (US);

Gordon A. Haller, Boise, ID (US);

Lequn Liu, Boise, ID (US);

Inventors:

Vladimir Mikhalev, Boise, ID (US);

Jim Fulford, Meridian, ID (US);

Yongjun Jeff Hu, Boise, ID (US);

Gordon A. Haller, Boise, ID (US);

Lequn Liu, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823462 (2013.01); H01L 21/76834 (2013.01); H01L 21/02164 (2013.01); H01L 21/02107 (2013.01); H01L 21/823481 (2013.01); H01L 21/76832 (2013.01); H01L 21/02282 (2013.01); H01L 21/265 (2013.01); H01D 21/76224 (2013.01); H01L 21/823425 (2013.01); H01L 29/66575 (2013.01); H01L 29/78 (2013.01); H01L 29/7846 (2013.01);
Abstract

Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.


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