The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2014
Filed:
Mar. 15, 2013
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Navneet Jain, Sunnyvale, CA (US);
Paul D. Mesa, Sunnyvale, CA (US);
Qinglei Wang, San Jose, CA (US);
Qi Xiang, Sunnyvale, CA (US);
Mahbub Rashed, Cupertino, CA (US);
Assignee:
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5068 (2013.01);
Abstract
A parameterized cell for planar and finFET designs is provided. A parameterized cell (Pcell) describing a planar design is integrated with fin-based design criteria, including fin pitch. For material regions in a planar design that have a corresponding region in a fin design, a quantized value based on the fin pitch is computed. The material can include regions such as active area silicon, contact regions, and local interconnect regions.