The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2014
Filed:
Jan. 01, 2013
Sundar Iyer, Palo Alto, CA (US);
Shang-tse Chuang, Los Altos, CA (US);
Thu Nguyen, Palo Alto, CA (US);
Sanjeev Joshi, San Jose, CA (US);
Adam Kablanian, Los Altos Hills, CA (US);
Kartik Mohanram, Pittsburgh, PA (US);
Sundar Iyer, Palo Alto, CA (US);
Shang-Tse Chuang, Los Altos, CA (US);
Thu Nguyen, Palo Alto, CA (US);
Sanjeev Joshi, San Jose, CA (US);
Adam Kablanian, Los Altos Hills, CA (US);
Kartik Mohanram, Pittsburgh, PA (US);
Memoir Systems, Inc., Santa Clara, CA (US);
Abstract
Static random access memory (SRAM) circuits are used in most digital integrated circuits to store data. To handle multiple memory users, an efficient dual port six transistor (6T) SRAM memory cell is proposed. The dual port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the SRAM cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two reads in a single cycle using spatial domain multiplexing. Writes can be handled faster that read operations such that two writes can be handled in a single cycle using time division multiplexing. To further improve the operation of the dual port 6T SRAM cell a number of algorithmic techniques are used to improve the operation of the memory system.