The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2014

Filed:

Feb. 27, 2013
Applicants:

Ki-jae Huh, Seoul, KR;

Satoru Yamada, Seoul, KR;

Jun-hee Lim, Seoul, KR;

Sung-ho Jang, Hwaseong-si, KR;

Inventors:

Ki-Jae Huh, Seoul, KR;

Satoru Yamada, Seoul, KR;

Jun-Hee Lim, Seoul, KR;

Sung-Ho Jang, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/04 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 29/4236 (2013.01); H01L 29/41766 (2013.01); H01L 29/78 (2013.01); H01L 27/04 (2013.01);
Abstract

A semiconductor device including a buried cell array transistor and an electronic device including the same are provided. The device includes a field region in a substrate and the filed region defines an active region. A first source/drain region and a second source/drain region are in the active region. A gate trench is between the first and second source/drain regions, and in the active region and the field region. A gate structure is within the gate trench. The gate structure includes a gate electrode, an insulating gate capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an insulating metal-containing material layer between the insulating gate capping pattern and the active region.


Find Patent Forward Citations

Loading…