The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2014
Filed:
Jun. 04, 2004
Richard Fastow, Cupertino, CA (US);
Zhigang Wang, Sunnyvale, CA (US);
Yue-song He, San Jose, CA (US);
Kazuhiro Mizutani, Sunnyvale, CA (US);
Pavel Fastenko, Sunnyvale, CA (US);
Richard Fastow, Cupertino, CA (US);
Zhigang Wang, Sunnyvale, CA (US);
Yue-Song He, San Jose, CA (US);
Kazuhiro Mizutani, Sunnyvale, CA (US);
Pavel Fastenko, Sunnyvale, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile