The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2014

Filed:

May. 31, 2013
Applicant:

Novellus Systems, Inc., Fremont, CA (US);

Inventors:

Keith Fox, Tigard, OR (US);

Dong Niu, West Linn, OR (US);

Joseph L. Womack, Tigard, OR (US);

Assignee:

Novellus Systems, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/205 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02694 (2013.01); H01L 21/02274 (2013.01); H01L 21/02211 (2013.01); H01L 21/02507 (2013.01); H01L 21/0217 (2013.01); H01L 21/02123 (2013.01); H01L 21/02532 (2013.01);
Abstract

The method and apparatus disclosed herein relate to preparing a stack structure for an electronic device on a semiconductor substrate. A particularly beneficial application of the method is in reduction of internal stress in a stack containing multiple layers of silicon. Typically, though not necessarily, the internal stress is a compressive stress, which often manifests as wafer bow. In some embodiments, the method reduces the internal stress of a work piece by depositing phosphorus doped silicon layers having low internal compressive stress or even tensile stress. The method and apparatus disclosed herein can be used to reduce compressive bow in stacks containing silicon.


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