The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2014

Filed:

Jan. 27, 2009
Applicants:

Hong Won Kim, Suwon-si, KR;

Sung Yi, Suwon-si, KR;

Tae Sung Jeong, Hwaseong-si, KR;

Joon Seok Kang, Suwon-si, JP;

Inventors:

Hong Won Kim, Suwon-si, KR;

Sung Yi, Suwon-si, KR;

Tae Sung Jeong, Hwaseong-si, KR;

Joon Seok Kang, Suwon-si, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/30 (2006.01); H01L 23/00 (2006.01); H05K 1/18 (2006.01); H01L 21/683 (2006.01); H05K 3/42 (2006.01);
U.S. Cl.
CPC ...
H05K 1/185 (2013.01); H01L 24/96 (2013.01); H01L 2924/01078 (2013.01); H05K 2201/10674 (2013.01); H05K 2201/10515 (2013.01); H01L 2924/01029 (2013.01); H01L 24/18 (2013.01); H01L 24/82 (2013.01); H01L 2924/01059 (2013.01); H05K 3/426 (2013.01); H01L 2224/18 (2013.01); H01L 2924/01033 (2013.01); H01L 21/6835 (2013.01); H01L 2924/01006 (2013.01); H05K 2203/1461 (2013.01);
Abstract

The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof and provides a chip embedded printed circuit board including: an insulating layer having vias formed therethrough; a first chip and a second chip embedded in the insulating layer and having pads, which are respectively exposed to upper and lower surfaces of the insulating layer, on one surfaces thereof; an upper pattern formed on the upper surface of the insulating layer to be connected to the pads of the first chip and the vias; and a lower pattern formed on the lower surface of the insulating layer to be connected to the pads of the second chip and the vias. Also, the present invention provides a manufacturing method of a chip embedded printed circuit board.


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