The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2014

Filed:

Jun. 28, 2012
Applicants:

Chuan-jin Shiu, Zhongli, TW;

Po-shen Lin, New Taipei, TW;

Yi-ming Chang, Pingzhen, TW;

Inventors:

Chuan-Jin Shiu, Zhongli, TW;

Po-Shen Lin, New Taipei, TW;

Yi-Ming Chang, Pingzhen, TW;

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 21/00 (2006.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14618 (2013.01); H01L 27/1463 (2013.01);
Abstract

An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a light shielding layer disposed on the second surface of the substrate and directly contacting with the conducting layer, wherein the light shielding layer has a light shielding rate of more than about 80% and has at least an opening exposing the conducting layer; and a conducting bump disposed in the opening of the light shielding layer to electrically contact with the conducting layer, wherein all together the light shielding layer and the conducting bump substantially and completely cover the second surface of the substrate.


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