The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2014

Filed:

Sep. 01, 2011
Applicants:

Hua Song, Wuxi, CN;

Hsiao-chia Wu, Wuxi, CN;

Tse-huang Lo, Wuxi, CN;

Inventors:

Hua Song, Wuxi, CN;

Hsiao-Chia Wu, Wuxi, CN;

Tse-Huang Lo, Wuxi, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/425 (2006.01); H01L 21/265 (2006.01); H01L 21/74 (2006.01); H01L 29/02 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 21/265 (2013.01); H01L 21/74 (2013.01); H01L 29/02 (2013.01); H01L 21/26513 (2013.01); H01L 29/0821 (2013.01);
Abstract

The present disclosure provides a semiconductor device and a method for fabricating a semiconductor buried layer. The method includes: preparing a substrate which includes a first oxide layer; forming a first buried layer region in the surface of the substrate by using a photoresist layer with a first buried layer region pattern as a mask, in which a doping state of the first buried layer region is different from a doping state of other region of the substrate; forming a second oxide layer on the surface of the substrate and the first buried layer region; and forming a second buried layer region in the surface of the substrate through self alignment process by using the second oxide layer as a mask. The method disclosed by the present disclosure reduces the complexity of the buried layer procedures and the cost thereof, as well as the probability of crystal defects.


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Song, Hua. (2014). Semiconductor device and method for fabricating semiconductor buried layer (U.S. Patent No. 8889535). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8889535

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