The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8885305 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 11, 2014

Filed:

Apr. 25, 2012
Applicants:

Yi Shan, Singapore, SG;

Manjunatha Prabhu, Singapore, SG;

Inventors:

Yi Shan, Singapore, SG;

Manjunatha Prabhu, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 9/02 (2006.01); H05K 3/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

A high performance ESD protection circuit is provided. Embodiments include a circuit having an RC clamp circuit including a first NMOS transistor having a first source, drain, and gate, a current mirror circuit including first and second PMOS transistors having a second and third source, drain, and gate, respectively, and an SCR circuit including a first P+ contact. The first source is coupled to a ground rail, the first drain is coupled to the second drain, second gate, and third gate, the second and third sources are coupled to a power rail, and the third drain is coupled to the first P+ contact, wherein during an ESD event the first NMOS and PMOS transistors turn on to discharge a first current to the ground rail, and the current mirror provides a second current to the first P+ contact for turning on the SCR.


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Shan, Yi. (2014). Method and apparatus for esd circuits (U.S. Patent No. 8885305). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8885305

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