The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2014

Filed:

May. 13, 2013
Applicants:

Amanda E. Schuckman, Scottsdale, AZ (US);

Mark S. Hlad, Chandler, AZ (US);

Inventors:

Amanda E. Schuckman, Scottsdale, AZ (US);

Mark S. Hlad, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 21/76802 (2013.01);
Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for providing void-free filled interconnect structures in a dielectric layer of a package assembly. In one embodiment, the method for providing a void-free filled interconnect structure may include forming a through hole through a layer of a package substrate, and depositing a conductive material to fill the through hole. Depositing the conductive material may be performed while gradually increasing a current density of the conductive material and correspondingly changing a flow rate of the conductive material. Other embodiments may be described and/or claimed.


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