The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2014
Filed:
Mar. 28, 2014
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Yi-Tang Lin, Hsinchu, TW;
Cheok-Kei Lei, Andar AC, MO (US);
Shu-Yu Chen, Hsinchu, TW;
Yu-Ning Chang, Hsinchu, TW;
Hsiao-Hui Chen, Hsinchu, TW;
Chih-Sheng Chang, Hsinchu, TW;
Chien-Wen Chen, Hsinchu, TW;
Clement Hsingjen Wann, Carmel, NY (US);
Abstract
A method and layout generating machine for generating a layout for a device having FinFETs from a first layout for a device having planar transistors are disclosed. A planar layout with a plurality of FinFET active areas is received and corresponding FinFET active areas are generated with active area widths. Mandrels are generated according to the active area widths and adjusted such that a beta ratio of a beta number for each FinFET active area to a beta number for each corresponding planar active area is within a predetermined beta ratio range.