The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2014

Filed:

Dec. 31, 2007
Applicants:

Muhammad M. Khellah, Tigard, OR (US);

Christopher Wilkerson, Portland, OR (US);

Alaa R. Alameldeen, Aloha, OR (US);

Bibiche M. Geuskens, Beaverton, OR (US);

Tanay Karnik, Portland, OR (US);

Vivek DE, Beaverton, OR (US);

Gunjan H. Pandya, Beaverton, OR (US);

Inventors:

Muhammad M. Khellah, Tigard, OR (US);

Christopher Wilkerson, Portland, OR (US);

Alaa R. Alameldeen, Aloha, OR (US);

Bibiche M. Geuskens, Beaverton, OR (US);

Tanay Karnik, Portland, OR (US);

Vivek De, Beaverton, OR (US);

Gunjan H. Pandya, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and apparatus to reduce minimum operating voltage through a hybrid cache design are described. In one embodiment, a cache with different size bit cells may be used, e.g., to reduce minimum operating voltage of an integrated circuit device that includes the cache and possibly other logic (such as a processor). Other embodiments are also described.


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