The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2014
Filed:
May. 04, 2011
Applicants:
Hao-yu Chen, Kaohsiung, TW;
Chang-yun Chang, Taipei, TW;
Di-hong Lee, Austin, TX (US);
Fu-liang Yang, Hsin-Chu, TW;
Inventors:
Hao-Yu Chen, Kaohsiung, TW;
Chang-Yun Chang, Taipei, TW;
Di-Hong Lee, Austin, TX (US);
Fu-Liang Yang, Hsin-Chu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/786 (2006.01); H01L 21/84 (2006.01); H01L 21/762 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78603 (2013.01); H01L 21/84 (2013.01); H01L 21/76267 (2013.01); H01L 21/76283 (2013.01); H01L 27/1203 (2013.01);
Abstract
An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.