The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2014

Filed:

Nov. 01, 2012
Applicants:

Ling MA, Redondo Beach, CA (US);

Andrew N. Sawle, E. Grinstead, GB;

David Paul Jones, South Glamorgan, GB;

Timothy D. Henson, Torrance, CA (US);

Niraj Ranjan, El Segundo, CA (US);

Vijay Viswanathan, Apex, NC (US);

Omar Hassen, Irvine, CA (US);

Inventors:

Ling Ma, Redondo Beach, CA (US);

Andrew N. Sawle, E. Grinstead, GB;

David Paul Jones, South Glamorgan, GB;

Timothy D. Henson, Torrance, CA (US);

Niraj Ranjan, El Segundo, CA (US);

Vijay Viswanathan, Apex, NC (US);

Omar Hassen, Irvine, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
Abstract

One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.


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