The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2014

Filed:

Oct. 05, 2012
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Ralf Otremba, Kaufbeuren, DE;

Josef Hoeglauer, Heimstetten, DE;

Gerhard Noebauer, Villach, AT;

Chooi Mei Chong, Melaka, MY;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
Abstract

A chip package is provided. The chip package includes a chip carrier, a voltage supply lead, a sensing terminal and a chip disposed over the chip carrier. The chip includes a first terminal and a second terminal, wherein the first terminal electrically contacts the chip carrier. The chip package also includes an electrically conductive element formed over the second terminal, the electrically conductive element electrically coupling the second terminal to the voltage supply lead and the sensing terminal.


Find Patent Forward Citations

Otremba, Ralf. (2014). Chip arrangements, a chip package and a method for manufacturing a chip arrangement (U.S. Patent No. 8853835). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8853835

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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