The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2014

Filed:

Nov. 02, 2011
Applicants:

Byung-lyul Park, Seoul, KR;

Gil-heyun Choi, Seoul, KR;

Suk-chul Bang, Yongin-Si, KR;

Kwang-jin Moon, Suwon-Si, KR;

Dong-chan Lim, Suwon-Si, KR;

Deok-young Jung, Seoul, KR;

Inventors:

Byung-Lyul Park, Seoul, KR;

Gil-Heyun Choi, Seoul, KR;

Suk-Chul Bang, Yongin-Si, KR;

Kwang-Jin Moon, Suwon-Si, KR;

Dong-Chan Lim, Suwon-Si, KR;

Deok-Young Jung, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 23/40 (2006.01); H01L 21/768 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76898 (2013.01); H01L 2225/06541 (2013.01); H01L 2224/16 (2013.01); H01L 25/18 (2013.01); H01L 2225/06513 (2013.01); H01L 25/0657 (2013.01); H01L 21/76801 (2013.01);
Abstract

For forming a semiconductor device, a via structure is formed through at least one dielectric layer and at least a portion of a substrate. In addition, a protective buffer layer is formed onto the via structure. Furthermore, a conductive structure for an integrated circuit is formed over the substrate after forming the via structure and the protective buffer layer, with the conductive structure not being formed over the via structure. Thus, deterioration of the conductive and via structures is minimized.


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