The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2014

Filed:

Mar. 27, 2012
Applicants:

Yen-liang Chen, Zhubei, TW;

Te-chih Huang, Chu-Bei, TW;

Chen-ming Wang, Kaohsiung, TW;

Chih-ming KE, Hsinchu, TW;

Tsai-sheng Gau, Hsinchu, TW;

Inventors:

Yen-Liang Chen, Zhubei, TW;

Te-Chih Huang, Chu-Bei, TW;

Chen-Ming Wang, Kaohsiung, TW;

Chih-Ming Ke, Hsinchu, TW;

Tsai-Sheng Gau, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/68 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of determining overlay error in semiconductor device fabrication includes receiving an image of an overlay mark formed on a substrate. The received image is separated into a first image and a second image, where the first image includes representations of features formed on a first layer of the substrate and the second image includes representations of the features formed on a second layer of the substrate. A quality indicator is determined for the first image and a quality indicator is determined for the second image. In an embodiment, the quality indicators include asymmetry indexes.


Find Patent Forward Citations

Chen, Yen-Liang. (2014). System and method for alignment in semiconductor device fabrication (U.S. Patent No. 8837810). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8837810

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