The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2014
Filed:
Aug. 02, 2013
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventors:
Prashant Dubey, Greater Noida, IN;
Guarav Ahuja, New Delhi, IN;
Sanjay Kumar Yadav, Greater Noida, IN;
Amit Khanuja, New Delhi, IN;
Assignee:
Synopsys, Inc., Mountain View, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/12 (2006.01); H02M 3/07 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); H02M 3/07 (2013.01); G11C 7/1084 (2013.01); G11C 7/1096 (2013.01);
Abstract
An integrated circuit for generating a negative bitline voltage comprises a bitline connectable to a memory cell and a multitude of capacitors arranged in groups thereof connected to the bitline. A step signal generator can generate a consecutive sequence of step signals to be applied to a group of capacitors. The circuit may be part of an integrated memory circuit device to drive the bitline to a negative voltage to implement a write assist scheme.