The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2014

Filed:

Jun. 03, 2013
Applicant:

Unisantis Electronics Singapore Pte. Ltd., Singapore, SG;

Inventors:

Fujio Masuoka, Tokyo, JP;

Nozomu Harada, Tokyo, JP;

Hiroki Nakamura, Tokyo, JP;

Xiang Li, Singapore, SG;

Xinpeng Wang, Singapore, SG;

Zhixian Chen, Singapore, SG;

Aashit Ramachandra Kamath, Singapore, SG;

Navab Singh, Singapore, SG;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 29/78642 (2013.01); H01L 29/0676 (2013.01); H01L 29/66795 (2013.01); H01L 29/775 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66742 (2013.01);
Abstract

A method for producing a semiconductor device includes a first step including forming a planar silicon layer and forming first and second pillar-shaped silicon layers; a second step including forming a gate insulating film around each of the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, the thickness of the polysilicon film being smaller than half of a distance between the first and second pillar-shaped silicon layers, forming a third resist, and forming a gate line; and a third step including depositing a fourth resist so that a portion of the polysilicon film on an upper side wall of each of the first and second pillar-shaped silicon layers is exposed, removing the exposed portion of the polysilicon film, removing the fourth resist, and removing the metal film to form first and second gate electrodes.


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