The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2014

Filed:

Nov. 07, 2012
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Pratyush Kamal, San Diego, CA (US);

Esin Terzioglu, San Diego, CA (US);

Foua Vang, Lemon Grove, CA (US);

Prayag Bhanubhai Patel, San Diego, CA (US);

Giridhar Nallapati, San Diego, CA (US);

Animesh Datta, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 27/118 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 29/66545 (2013.01); H01L 27/11807 (2013.01); H01L 27/0207 (2013.01); H01L 2027/11831 (2013.01);
Abstract

A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.


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