The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2014

Filed:

May. 10, 2010
Applicants:

Shyue Seng Tan, Singapore, SG;

Lee Wee Teo, Singapore, SG;

Inventors:

Shyue Seng Tan, Singapore, SG;

Lee Wee Teo, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/26506 (2013.01); H01L 29/7833 (2013.01); H01L 29/7848 (2013.01); H01L 21/265 (2013.01); H01L 29/6656 (2013.01); H01L 29/6659 (2013.01); H01L 29/7843 (2013.01);
Abstract

A method for fabricating a semiconductor device is presented. The method comprises providing a gate stack including a gate dielectric and gate electrode over a substrate. Stressor regions comprising stressor material incorporated into substitutional sites of the substrate are formed within the substrate on opposed sides of the gate stack. A first stressor layer having a first stress value is formed over the semiconductor device after forming the stressor regions followed by an anneal to memorize at least a portion of the first stress value in the semiconductor device, wherein the anneal is conducted at a low temperature.


Find Patent Forward Citations

Loading…