The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8835306 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 16, 2014

Filed:

Feb. 01, 2013
Applicant:

Globalfoundries, Inc., Grand Cayman, KY;

Inventors:

Errol Todd Ryan, Clifton Park, NY (US);

Kunaljeet Tanwar, Slingerlands, NY (US);

Assignee:

GLOBALFOUNDRIES, Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/768 (2013.01);
Abstract

A method for fabricating integrated circuits includes providing a substrate including a protecting layer over an oxide layer and etching a recess through the protecting layer and into the oxide layer. A barrier material is deposited over the substrate to form a barrier layer including a first region in the recess and a second region outside the recess. A conductive material is deposited over the barrier layer and forms an embedded electrical interconnect in the recess and an overburden region outside the recess. The overburden region of the conductive material is removed and a portion of the embedded electrical interconnect is recessed. Thereafter, the barrier layer is etched to remove the second region of the barrier layer and to recess a portion of the first region of the barrier layer. After etching the barrier layer, the protecting layer is removed from the oxide layer.


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