The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2014

Filed:

Nov. 24, 2010
Applicants:

Hamid Assarpour, Arlington, MA (US);

Mike Craren, Holliston, MA (US);

Rich Modelski, Hollis, NH (US);

Inventors:

Hamid Assarpour, Arlington, MA (US);

Mike Craren, Holliston, MA (US);

Rich Modelski, Hollis, NH (US);

Assignee:

Avaya Inc., Basking Ridge, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/06 (2006.01); H04L 12/56 (2006.01); H04L 12/46 (2006.01);
U.S. Cl.
CPC ...
H04L 12/4625 (2013.01); H04L 45/54 (2013.01);
Abstract

A method and apparatus for efficient memory bank utilization in multi-threaded packet processors is presented. A plurality of memory access requests, are received and are buffered by a plurality of memory First In First Out (FIFO) buffers, each of the memory FIFO buffers in communication with a memory controller. The memory access requests are distributed evenly across said memory banks by way of the memory controller. This reduces and/or eliminates memory latency which can occur when sequential memory operations are performed on the same memory bank.


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