The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2014
Filed:
Jul. 09, 2012
Rajeevan Mahadevan, Toronto, CA;
Antonios Pialis, Scarborough, CA;
Robert Wang, Whitby, CA;
Navid Yaghini, Pickering, CA;
Rafal Karakiewicz, Toronto, CA;
Raymond Kwok Kei Tang, Thornhill, CA;
Sida Shen, North York, CA;
Mark Andruchow, Toronto, CA;
Zhuobin LI, Toronto, CA;
Nicola Pantaleo, Toronto, CA;
Rajeevan Mahadevan, Toronto, CA;
Antonios Pialis, Scarborough, CA;
Robert Wang, Whitby, CA;
Navid Yaghini, Pickering, CA;
Rafal Karakiewicz, Toronto, CA;
Raymond Kwok Kei Tang, Thornhill, CA;
Sida Shen, North York, CA;
Mark Andruchow, Toronto, CA;
Zhuobin Li, Toronto, CA;
Nicola Pantaleo, Toronto, CA;
Intel Corporation, Santa Clara, CA (US);
Abstract
A system and method providing power supply rejection. One embodiment provides for power supply rejection in PLL or DLL circuitry. First subcircuitry provides second subcircuitry a supply voltage which is a filtered version of power from an external source. The first subcircuitry includes a first field effect transistor and a first low pass filter coupled to receive a signal from the external power source during operation of the second subcircuitry. The filter is coupled to provide a filtered version of the power source signal to the gate of the first transistor, so that when a first source/drain region of the first transistor is connected to receive power from the external source and the gate of the first transistor receives the filtered version of the power source signal, the second source/drain region of the first transistor provides a first modified version of the power received from the external source.