The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2014

Filed:

Aug. 20, 2010
Applicants:

Tuung Luoh, Taipei, TW;

Ming Da Cheng, Tonfene, TW;

Chin-ta Su, Yunli, TW;

Tahone Yang, Miaoli, TW;

Kuang-chao Chen, Taipei, TW;

Inventors:

Tuung Luoh, Taipei, TW;

Ming Da Cheng, Tonfene, TW;

Chin-Ta Su, Yunli, TW;

Tahone Yang, Miaoli, TW;

Kuang-Chao Chen, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76885 (2013.01); H01L 21/76852 (2013.01); H01L 23/53223 (2013.01);
Abstract

Methods for fabricating conductive metal lines of a semiconductor device are described herein. In one embodiment, such a method may comprise depositing a conductive material over a substrate, and depositing a first barrier layer on the conductive layer. Such a method may also comprise patterning a mask on the first barrier layer, the pattern comprising a layout of the conductive lines. Such an exemplary method may also comprise etching the conductive material and the first barrier layer using the patterned mask to form the conductive lines. In addition, a low temperature post-flow may be performed on the structure. The method may also include depositing a dielectric material over and between the patterned conductive lines.


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