The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2014
Filed:
Aug. 30, 2013
Imec, Leuven, BE;
Taiwan Semiconductor Manufacturing Company, Ltd., HsinChu, TW;
Globalfoundries Inc., Grand Cayman, KY;
Liesbeth Witters, Everberg, BE;
Rita Vos, Tremelo, BE;
David Brunco, Hillsboro, OR (US);
Marcus Johannes Henricus Van Dal, Heverlee, BE;
IMEC, Leuven, BE;
Taiwan Semiconductor Manufacturing Company, Ltd., HsinChu, TW;
GLOBALFOUNDRIES, Inc., Grand Cayman, KY;
Abstract
A method for manufacturing a transistor device is provided, the transistor device comprising a germanium based channel layer, the method comprising providing a gate structure on the germanium comprising channel layer provided on a substrate, the gate structure being provided between a germanium based source area and a germanium based drain area at opposite sides of the germanium comprising channel layer; providing a capping layer on the germanium based source and the germanium based drain area, the capping layer comprising Si and Ge; depositing a metal layer on the capping layer; performing a temperature step, thereby transforming at least part of the capping layer into a metal germano-silicide which is not soluble in a predetermined etchant adapted for dissolving the metal; selectively removing non-consumed metal from the substrate by means of the predetermined etchant; and providing a premetal dielectric layer.