The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2014
Filed:
Jul. 06, 2011
Wei-che Tsao, Tainan, TW;
Chia-lin Hsu, Tainan, TW;
Jen-chieh Lin, Kaohsiung, TW;
Teng-chun Tsai, Tainan, TW;
Hsin-kuo Hsu, Kaohsiung, TW;
Ya-hsueh Hsieh, Kaohsiung, TW;
Ren-peng Huang, Changhua County, TW;
Chih-hsien Chen, Miaoli County, TW;
Wen-chin Lin, Tainan, TW;
Yung-lun Hsieh, Tainan, TW;
Wei-Che Tsao, Tainan, TW;
Chia-Lin Hsu, Tainan, TW;
Jen-Chieh Lin, Kaohsiung, TW;
Teng-Chun Tsai, Tainan, TW;
Hsin-Kuo Hsu, Kaohsiung, TW;
Ya-Hsueh Hsieh, Kaohsiung, TW;
Ren-Peng Huang, Changhua County, TW;
Chih-Hsien Chen, Miaoli County, TW;
Wen-Chin Lin, Tainan, TW;
Yung-Lun Hsieh, Tainan, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.