The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2014

Filed:

Nov. 02, 2012
Applicant:

Shinko Electric Industries Co., Ltd., Nagano-ken, JP;

Inventors:

Noriyoshi Shimizu, Nagano, JP;

Akio Rokugawa, Nagano, JP;

Osamu Inoue, Nagano, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/29 (2006.01); H01L 25/10 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 21/56 (2006.01); H01L 23/48 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H05K 1/18 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 25/105 (2013.01); H01L 23/3128 (2013.01); H01L 2225/06517 (2013.01); H01L 24/48 (2013.01); H01L 23/49827 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/32145 (2013.01); H01L 25/0657 (2013.01); H01L 2225/1035 (2013.01); H01L 2224/48091 (2013.01); H01L 24/32 (2013.01); H01L 2924/15311 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/32225 (2013.01); H01L 21/563 (2013.01); H01L 2924/18162 (2013.01); H01L 23/48 (2013.01); H01L 2225/06558 (2013.01); H01L 23/5389 (2013.01); H05K 1/186 (2013.01); H01L 2224/16227 (2013.01); H01L 21/568 (2013.01); H01L 24/16 (2013.01); H01L 2224/48227 (2013.01); H01L 2924/3511 (2013.01); H01L 24/19 (2013.01); H01L 2225/1058 (2013.01); H05K 3/4682 (2013.01);
Abstract

A semiconductor package includes a semiconductor chip, a first insulating layer formed to cover the semiconductor chip, a wiring structure formed on the first insulating layer. The wiring structure has an alternately layered configuration including wiring layers electrically connected to the semiconductor chip and interlayer insulating layers each located between one of the wiring layers and another. The interlayer insulating layers include an outermost interlayer insulating layer located farthest from a surface of the first insulating layer. A groove formed in the outermost interlayer insulating layer passes through the outermost interlayer insulating layer in a thickness direction.


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