The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2014

Filed:

Dec. 28, 2012
Applicant:

Shanghai Huali Microelectronics Corporation, Shanghai, CN;

Inventors:

Chuan Ren, Shanghai, CN;

Zhi Wang, Shanghai, CN;

HsuSheng Chang, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/31 (2006.01); H01L 21/3205 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0603 (2013.01); H01L 21/3205 (2013.01); H01L 21/022 (2013.01);
Abstract

A dummy wafer structure and a method of forming the same are disclosed. The dummy wafer structure includes: a silicon substrate; a silicon nitride layer over the silicon substrate; and a silicon dioxide layer over the silicon nitride layer. The method includes: a first step of forming a silicon nitride layer over a silicon substrate so as to form a silicon-silicon nitride structure; and a second step of forming a silicon dioxide layer over the silicon-silicon nitride structure obtained in the first step so as to form a silicon-silicon nitride-silicon dioxide structure. Dummy wafers with this special structure are able to avoid deposition rate inconsistency in a polysilicon deposition process and are capable of avoiding conventional dummy wafers' adverse effect on deposit layer thicknesses of process wafers and hence providing the process wafers with deposit layers having a high inter-wafer uniformity.


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