The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2014

Filed:

Nov. 16, 2010
Applicants:

Shamanna M. Datta, Hillsboro, OR (US);

Mahesh S. Natu, Sunnyvale, CA (US);

Inventors:

Shamanna M. Datta, Hillsboro, OR (US);

Mahesh S. Natu, Sunnyvale, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/24 (2006.01); G06F 21/57 (2013.01); G06F 21/00 (2013.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 21/575 (2013.01); G06F 21/57 (2013.01); G06F 21/00 (2013.01); G06F 11/0793 (2013.01);
Abstract

Methods and systems to perform platform security in conjunction with hardware-base root of trust logic are presented. In one embodiment, a method includes determining whether a status from an authenticated code module is indicative of an error or not. The method further includes determining whether the hardware-based root of trust logic is enabled based on content in a non-volatile memory location. If the hardware-based root of trust is enabled and the status is indicative of an error, the method further includes writing to the non-volatile memory location to disable hardware-based root of trust logic during a next boot sequence. In one embodiment, a platform initializes and uses the trusted platform module in conjunction with the hardware-based root of trust logic or with a platform-based root of trust logic.


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