The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2014
Filed:
Feb. 07, 2011
Rinji Sugino, San Jose, CA (US);
Bradley Marc Davis, Mountain View, CA (US);
Lei Xue, Milpitas, CA (US);
Kenichi Ohtsuka, Sunnyvale, CA (US);
Rinji Sugino, San Jose, CA (US);
Bradley Marc Davis, Mountain View, CA (US);
Lei Xue, Milpitas, CA (US);
Kenichi Ohtsuka, Sunnyvale, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
A method for semiconductor device fabrication is provided. The present invention is directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. At least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes.