The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2014
Filed:
May. 07, 2012
Lei Yuan, Sunnyvale, CA (US);
Jin Cho, Palo Alto, CA (US);
Jongwook Kye, Pleasanton, CA (US);
Harry J. Levinson, Saratoga, CA (US);
Lei Yuan, Sunnyvale, CA (US);
Jin Cho, Palo Alto, CA (US);
Jongwook Kye, Pleasanton, CA (US);
Harry J. Levinson, Saratoga, CA (US);
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
Abstract
One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.