The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2014

Filed:

Jul. 25, 2012
Applicants:

Harry-hak-lay Chuang, Singapore, SG;

Kong-beng Thei, Hsin-Chu, TW;

Jen-bin Hsu, Taoyuan, TW;

Chung Long Cheng, Hsin-Chu, TW;

Mong-song Liang, Hsin-Chu, TW;

Inventors:

Harry-Hak-Lay Chuang, Singapore, SG;

Kong-Beng Thei, Hsin-Chu, TW;

Jen-Bin Hsu, Taoyuan, TW;

Chung Long Cheng, Hsin-Chu, TW;

Mong-Song Liang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.


Find Patent Forward Citations

Chuang, Harry-Hak-Lay. (2014). Layout methods of integrated circuits having unit mos devices (U.S. Patent No. 8803202). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8803202

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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