Clock control for reducing timing exceptions in scan testing of an integrated circuit

Abstract

An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises a clock tree having clock signal lines, and clock control elements arranged in respective selected ones of the clock signal lines of the clock tree, where the clock control elements are configured to separate at least one synchronous clock domain into multiple asynchronous clock domains during scan testing. The clock control elements may be configured to reduce a number of timing exceptions produced during scan testing relative to a number of timing exceptions that would otherwise be produced if scan testing were performed using the synchronous clock domain.