The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2014

Filed:

Jun. 22, 2011
Applicants:

Cheng-hsien Cheng, Hsinchu, TW;

Wen-jer Tsai, Hsinchu, TW;

Shih-guei Yan, Hsinchu, TW;

Chih-chieh Cheng, Hsinchu, TW;

Jyun-siang Huang, Hsinchu, TW;

Inventors:

Cheng-Hsien Cheng, Hsinchu, TW;

Wen-Jer Tsai, Hsinchu, TW;

Shih-Guei Yan, Hsinchu, TW;

Chih-Chieh Cheng, Hsinchu, TW;

Jyun-Siang Huang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 21/336 (2006.01); H01L 27/115 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7923 (2013.01); H01L 27/11578 (2013.01); H01L 29/7887 (2013.01); H01L 27/11551 (2013.01);
Abstract

A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer.


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