The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2014
Filed:
Aug. 09, 2011
Alan C. Seabaugh, South Bend, IN (US);
Patrick Fay, Granger, IN (US);
Huili (Grace) Xing, South Bend, IN (US);
Guangle Zhou, South Bend, IN (US);
Yeqing LU, Notre Dame, IN (US);
Mark A. Wistey, South Bend, IN (US);
Siyuranga Koswatta, Yorktown Heights, NY (US);
Alan C. Seabaugh, South Bend, IN (US);
Patrick Fay, Granger, IN (US);
Huili (Grace) Xing, South Bend, IN (US);
Guangle Zhou, South Bend, IN (US);
Yeqing Lu, Notre Dame, IN (US);
Mark A. Wistey, South Bend, IN (US);
Siyuranga Koswatta, Yorktown Heights, NY (US);
University of Notre Dame du Lac, Notre Dame, IN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A low voltage tunnel field effect transistor includes a p-n tunnel junction, a gate-dielectric, a gate, a source-contact, and a drain-contact. The p-n tunnel junction includes a depletion region interfacing together a source-layer and a drain-layer. The depletion region includes a source-tunneling-region of the source-layer and a drain-tunneling-region of the drain-layer. When no external electric field is imposed, the depletion region of the p-n tunnel junction has an internal electric field that substantially points towards the source-tunneling-region and the drain-tunneling-region. The gate-dielectric is interfaced directly onto the drain-tunneling-region such that the drain-tunneling-region is between the source-tunneling-region and the gate-dielectric. The gate is interfaced onto the gate-dielectric such that the gate is configured to impose an external electric field which is oriented substantially in parallel to the internal electric field of the depletion region.