The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2014
Filed:
Aug. 20, 2010
Michel J. Abou-khalil, Essex Junction, VT (US);
Shunhua T. Chang, South Burlington, VT (US);
Kiran V. Chatty, Williston, VT (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Junjun LI, Williston, VT (US);
Mujahid Muhammad, Essex Junction, VT (US);
Michel J. Abou-Khalil, Essex Junction, VT (US);
Shunhua T. Chang, South Burlington, VT (US);
Kiran V. Chatty, Williston, VT (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Junjun Li, Williston, VT (US);
Mujahid Muhammad, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction.