The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2014

Filed:

Mar. 11, 2011
Applicants:

Hong-chen Cheng, Hsin-Chu, TW;

Jung-ping Yang, Juibei, TW;

Chung-ji LU, Fongyuan, TW;

Derek C. Tao, Fremont, CA (US);

Cheng Hung Lee, Hsin-Chu, TW;

Hung-jen Liao, Hsin-Chu, TW;

Inventors:

Hong-Chen Cheng, Hsin-Chu, TW;

Jung-Ping Yang, Juibei, TW;

Chung-Ji Lu, Fongyuan, TW;

Derek C. Tao, Fremont, CA (US);

Cheng Hung Lee, Hsin-Chu, TW;

Hung-Jen Liao, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.


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