The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2014

Filed:

Nov. 12, 2012
Applicant:

Hong Kong Applied Science and Technology Research Institute Company Limited, Hong Kong, HK;

Inventors:

Pui Chung Simon Law, Hong Kong, HK;

Bin Xie, Hong Kong, HK;

Dan Yang, Hong Kong, HK;

Assignee:

Hong Kong Applied Science and Technology Research Institute Company Limited, Hong Kong Science Park, Shatin, New Territories, Hong Kong, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76898 (2013.01); H01L 21/56 (2013.01);
Abstract

This invention discloses a through-silicon via (TSV) structure for providing an electrical path between a first-side surface and a second-side surface of a silicon chip, and a method for fabricating the structure. In one embodiment, the TSV structure comprises a via penetrated through the chip from the first-side surface to the second-side surface, providing a first end on the first-side surface and a second end on the second-side surface. A local isolation layer is deposited on the via's sidewall and on a portion of the first-side surface surrounding the first end. The TSV structure further comprises a plurality of substantially closely-packed microstructures arranged to form a substantially non-random pattern and fabricated on at least the portion of the first-side surface covered by the local isolation layer for promoting adhesion of the local isolation layer to the chip. A majority of the microstructures has a depth of at least 1 μm.


Find Patent Forward Citations

Loading…