The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2014

Filed:

Jul. 15, 2011
Applicants:

Chung-sun Lee, Gunpo-si, KR;

Jung-hwan Kim, Bucheon-si, KR;

Yun-hyeok Im, Yongin-si, KR;

Ji-hwan Hwang, Asan-si, KR;

Hyon-chol Kim, Hwaseong-si, KR;

Kwang-chul Choi, Suwon-si, KR;

Eun-kyoung Choi, Bucheon-si, KR;

Tae-hong Min, Gumi-si, KR;

Inventors:

Chung-sun Lee, Gunpo-si, KR;

Jung-Hwan Kim, Bucheon-si, KR;

Yun-hyeok Im, Yongin-si, KR;

Ji-hwan Hwang, Asan-si, KR;

Hyon-chol Kim, Hwaseong-si, KR;

Kwang-chul Choi, Suwon-si, KR;

Eun-kyoung Choi, Bucheon-si, KR;

Tae-hong Min, Gumi-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01); H01L 25/065 (2006.01); H01L 25/10 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 2225/107 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/15311 (2013.01); H01L 25/0655 (2013.01); H01L 2924/09701 (2013.01); H01L 2225/1094 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48227 (2013.01); H01L 2924/3511 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/32145 (2013.01); H01L 25/105 (2013.01); H01L 2924/01087 (2013.01); H01L 2224/97 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/15331 (2013.01); H01L 2225/1023 (2013.01); H01L 2224/73253 (2013.01); H01L 2225/06565 (2013.01); H01L 2924/18161 (2013.01); H01L 24/97 (2013.01); H01L 2224/16225 (2013.01);
Abstract

A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.


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