The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2014
Filed:
Mar. 11, 2011
Chooi Pei Lim, Bayan Lepas, MY;
Jordan Plofsky, San Jose, CA (US);
Yee Liang Tan, Gelugor, MY;
Teik Tiong Toong, Simpang Ampat, MY;
Chooi Pei Lim, Bayan Lepas, MY;
Jordan Plofsky, San Jose, CA (US);
Yee Liang Tan, Gelugor, MY;
Teik Tiong Toong, Simpang Ampat, MY;
Altera Corporation, San Jose, CA (US);
Abstract
Systems including an input/output (I/O) stack and methods for fabricating such systems are described. In one implementation, the methods include stacking an I/O die including I/O elements and excluding a logic element. Also in one implementation, the methods further include stacking an integrated circuit die with respect to the I/O die. The integrated circuit includes logic elements and excludes an I/O element. The separation of the I/O die from the integrated circuit die provides various benefits, such as independent development of each of the dies and more space for the I/O elements on an I/O substrate of the I/O die compared to that in a conventional die. The increase in space allows new process generation of the integrated circuit die in which an increasing number of logic elements are fitted within the same surface area of a substrate of the integrated circuit die.