The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2014
Filed:
Oct. 08, 2013
Richard K. Eguchi, Austin, TX (US);
Daniel Hadad, Austin, TX (US);
Chen He, Austin, TX (US);
Katrina M. Prosperi, Austin, TX (US);
Jon W. Weilmann, Ii, Austin, TX (US);
Richard K. Eguchi, Austin, TX (US);
Daniel Hadad, Austin, TX (US);
Chen He, Austin, TX (US);
Katrina M. Prosperi, Austin, TX (US);
Jon W. Weilmann, II, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A non-volatile memory system includes a memory array and a memory controller. The memory controller is configured to perform a first array integrity read operation of the array until an error is detected. The controller is also configured to determine that the error is not error correction code (ECC) correctable. A first word line voltage associated with the error is characterized as being a first threshold voltage. The controller is further configured to perform a second array integrity read operation of the array. The second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value. Finally, the controller is configured to check a check sum value resulting from the second array integrity read operation to determine when an imminent failure in the memory array is indicated.