The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2014
Filed:
Mar. 07, 2007
Takashi Noma, Gunma, JP;
Shigeki Otsuka, Chiba, JP;
Yuichi Morita, Kanagawa, JP;
Kazuo Okada, Gunma, JP;
Hiroshi Yamada, Gunma, JP;
Katsuhiko Kitagawa, Gunma, JP;
Noboru Okubo, Saitama, JP;
Shinzo Ishibe, Gunma, JP;
Hiroyuki Shinogi, Gunma, JP;
Takashi Noma, Gunma, JP;
Shigeki Otsuka, Chiba, JP;
Yuichi Morita, Kanagawa, JP;
Kazuo Okada, Gunma, JP;
Hiroshi Yamada, Gunma, JP;
Katsuhiko Kitagawa, Gunma, JP;
Noboru Okubo, Saitama, JP;
Shinzo Ishibe, Gunma, JP;
Hiroyuki Shinogi, Gunma, JP;
Semiconductor Components Industries, LLC, Phoenix, AZ (US);
Abstract
A packaged semiconductor device is manufactured by a simplified manufacturing process, and is reduced in cost, in thickness and in size. A device component and a pad electrode connected with the device component are formed on a semiconductor substrate. A supporter is bonded to a top surface of the semiconductor substrate through an adhesive layer. Then, there is formed a protection layer that has an opening at a location corresponding to the pad electrode and covers a side surface and a back surface of the semiconductor substrate. A conductive terminal is formed on the pad electrode at the location corresponding to the opening formed in the protection layer. No wiring layer or conductive terminal is formed on the back surface of the semiconductor substrate. A conductive terminal is formed on a periphery of the supporter outside of and next to the side surface of the semiconductor substrate.